PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Plouchart, Jean-Olivier"

Author of the publication

copydeleteadd this publication to your clipboard
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits.

, , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jean-Noel Grad University of Stuttgart

Jean-Louis Hoslauer University of Stuttgart

Dr. Eric Jean Kervio University of Stuttgart

 

Other publications of authors with the same name

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. on Circuits and Systems, 61-I (8): 2243-2252 (2014)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (4): 996-1008 (2013)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)An Integrated RF Transceiver For Short-Range, High-Speed Digital Communications in Tte U-NII 5.X GHz Band, , , , , , , , and . (1998)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate., , , , , , , , , and 1 other author(s). ISLPED, page 434-439. ACM, (2003)Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits., , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS., , , , , , and . ISSCC, page 278-279. IEEE, (2009)Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS., , , , , , and . ISSCC, page 542-621. IEEE, (2007)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. on Circuits and Systems, 60-I (8): 2009-2017 (2013)