PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Nowick, Steven M."

Author of the publication

copydeleteadd this publication to your clipboard
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.

, , , , and . IEEE Trans. VLSI Syst., 18 (7): 1043-1056 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Steven Minden University of Stuttgart

Steven Presser University of Stuttgart

Steven Biele University of Stuttgart

Steven Jöns University of Stuttgart

Steven Scharr University of Stuttgart

 

Other publications of authors with the same name

Specification and Automatic Verification of Self-Timed Queues., , and . Formal Methods in System Design, 1 (1): 29-60 (1992)The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style., and . IEEE Trans. VLSI Syst., 15 (11): 1256-1269 (2007)ACM Journal on Emerging Technologies in Computing Systems., and . ACM Trans. Design Autom. Electr. Syst., 16 (1): 11 (2010)Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (1): 75-88 (2012)Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication., , and . ASYNC, page 186-195. IEEE Computer Society, (2007)Low-Latency Asynchronous FIFO's Using Token Rings., and . ASYNC, page 210-. IEEE Computer Society, (2000)A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors., , , and . NOCS, page 43-50. IEEE Computer Society, (2010)A low-latency asynchronous interconnection network with early arbitration resolution., , , and . ASP-DAC, page 329-336. IEEE, (2014)A correctness criterion for asynchronous circuit validation and optimization., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 13 (11): 1309-1318 (1994)Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (12): 1514-1521 (1997)