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Automated detection and verification of parity-protected memory elements., , , and . ICCAD, page 1-8. IEEE, (2014)Measurements for structural logic synthesis optimizations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (6): 665-674 (2003)Implicit enumeration of structural changes in circuit optimization., and . DAC, page 438-441. ACM, (2004)Statistical Fault Injection., , , , and . DSN, page 122-127. IEEE Computer Society, (2008)Stable Adaptive Schemes for System Identification and Control - Part II., and . IEEE Trans. Systems, Man, and Cybernetics, 4 (6): 552-560 (1974)Testing two-phase transition signaling based self-timed circuits in a synthesis environment., and . HLSS, page 104-111. ACM, (1994)Soft-error resilience of the IBM POWER6 processor input/output subsystem., , , , , , and . IBM Journal of Research and Development, 52 (3): 285-292 (2008)Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity., , , , and . VTS, page 1. IEEE Computer Society, (2013)Rethinking Processor Design: Parameter Correlations., , and . ICECS, page 156-159. IEEE, (2006)Combinatorial cell design for CMOS libraries., , , , and . Integration, 29 (1): 67-93 (2000)