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Disambiguation of "Matick, Richard E."

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A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)

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E. Zafeiriou

E. Garrelts

Richard Powers University of Stuttgart

Univ. -Prof. Dr. Richard Dipper University of Stuttgart

Richard Gozali University of Stuttgart

 

Other publications of authors with the same name

Modular nets (MNETS): A modular design methodology for computer timers.. IBM Journal of Research and Development, 42 (6): 813-830 (1998)Fast Low Power eDRAM Hierarchical Differential Sense Amplifier., and . J. Solid-State Circuits, 44 (2): 631-641 (2009)Comparison of analytic performance models using closed mean-value analysis versus open-queuing theory for estimating cycles per instruction of memory hierarchies.. IBM Journal of Research and Development, 47 (4): 495-517 (2003)Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory., , and . IBM Journal of Research and Development, 45 (6): 819-842 (2001)Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip., , and . IBM Journal of Research and Development, 33 (5): 524-539 (1989)Impact of Memory Systems on Computer Architecture and System Organization.. IBM Systems Journal, 25 (3/4): 274-305 (1986)All Points Addressable Raster Display Memory., , , and . IBM Journal of Research and Development, 28 (4): 379-392 (1984)Logic-based eDRAM: Origins and rationale for use., and . IBM Journal of Research and Development, 49 (1): 145-166 (2005)Architecture Implications in the Design of Microprocessors., and . IBM Systems Journal, 23 (3): 264-280 (1984)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)