%0 Journal Article %1 journals/jssc/KlimBRDFKLKWGKM09 %A Klim, Peter J. %A Barth, John %A Reohr, William R. %A Dick, David %A Fredeman, Gregory %A Koch, Gary %A Le, Hien M. %A Khargonekar, Aditya %A Wilcox, Pamela %A Golz, John %A Kuang, Jente B. %A Mathews, Abraham %A Law, Jethro C. %A Luong, Trong %A Ngo, Hung C. %A Freese, Ryan %A Hunter, Hillery C. %A Nelson, Erik %A Parries, Paul C. %A Kirihata, Toshiaki %A Iyer, Subramanian S. %D 2009 %J IEEE J. Solid State Circuits %K dblp %N 4 %P 1216-1226 %T A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#KlimBRDFKLKWGKM09 %V 44

@article{journals/jssc/KlimBRDFKLKWGKM09, added-at = {2022-02-25T00:00:00.000+0100}, author = {Klim, Peter J. and Barth, John and Reohr, William R. and Dick, David and Fredeman, Gregory and Koch, Gary and Le, Hien M. and Khargonekar, Aditya and Wilcox, Pamela and Golz, John and Kuang, Jente B. and Mathews, Abraham and Law, Jethro C. and Luong, Trong and Ngo, Hung C. and Freese, Ryan and Hunter, Hillery C. and Nelson, Erik and Parries, Paul C. and Kirihata, Toshiaki and Iyer, Subramanian S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23f6bbb86a13af04f01bd7692c73c9db7/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2014207}, interhash = {f0d7f07ff5c4b5be94b0e7b2b829d6a0}, intrahash = {3f6bbb86a13af04f01bd7692c73c9db7}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 4, pages = {1216-1226}, timestamp = {2022-03-01T06:21:56.000+0100}, title = {A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc44.html#KlimBRDFKLKWGKM09}, volume = 44, year = 2009 }