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Disambiguation of "Fazan, Pierre"

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I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.

, , , , , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Pierre Nacke University of Stuttgart

Dr. rer. nat. Pierre Eckold University of Stuttgart

Pierre Kuna University of Stuttgart

 

Other publications of authors with the same name

Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs., , , , , , , , , and 1 other author(s). ESSDERC, page 338-341. IEEE, (2012)Zero capacitor embedded memory technology for system on chip., , and . MTDT, page xxi-xxv. IEEE Computer Society, (2005)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration., , , , , , , , , and 2 other author(s). ICICDT, page 1-4. IEEE, (2015)Off-state stress degradation mechanism on advanced p-MOSFETs., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors., , , , , , , , , and 8 other author(s). ESSDERC, page 190-193. IEEE, (2013)Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks., , , , , , , , , and 2 other author(s). ESSDERC, page 242-245. IEEE, (2012)