Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors., , , , , , , , , and 8 other author(s). ESSDERC, page 190-193. IEEE, (2013)Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks., , , , , , , , , and 2 other author(s). ESSDERC, page 242-245. IEEE, (2012)Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements., , , , , , and . IEEE Trans. on Circuits and Systems, 59-II (7): 439-442 (2012)Experimental evidences and simulations of trap generation along a percolation path., , , , , , , , , and . ESSDERC, page 226-229. IEEE, (2015)CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies., , , , , , , , , and . IRPS, page 1-7. IEEE, (2019)Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs., , , , , , , , , and 1 other author(s). ESSDERC, page 330-333. IEEE, (2012)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)