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Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.

B. O'Sullivan, R. Ritzenthaler, G. Rzepa, Z. Wu, E. Litta, O. Richard, T. Conard, V. Machkaoutsan, P. Fazan, C. Kim, J. Franco, B. Kaczer, T. Grasser, A. Spessot, D. Linten, and N. Horiguchi. IRPS, page 1-8. IEEE, (2019)

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Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.B. Kaczer, J. Franco, P. Weckx, P. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais and 4 other author(s). Microelectronics Reliability, (2018)The defect-centric perspective of device and circuit reliability - From individual defects to circuits.B. Kaczer, J. Franco, P. Weckx, P. Roussel, E. Bury, M. Cho, R. Degraeve, D. Linten, G. Groeseneken, H. Kukner and 5 other author(s). ESSDERC, page 218-225. IEEE, (2015)Comphy - A compact-physics framework for unified modeling of BTI.G. Rzepa, J. Franco, B. O'Sullivan, A. Subirats, M. Simicic, G. Hellings, P. Weckx, M. Jech, T. Knobloch, M. Waltl and 4 other author(s). Microelectronics Reliability, (2018)Characterization and modeling of charge trapping: From single defects to devices.T. Grasser, G. Rzepa, M. Waltl, W. Gös, K. Rott, G. Rott, H. Reisinger, J. Franco, and B. Kaczer. ICICDT, page 1-4. IEEE, (2014)Identification of oxide defects in semiconductor devices: A systematic approach linking DFT to rate equations and experimental evidence.W. Gös, Y. Wimmer, A. El-Sayed, G. Rzepa, M. Jech, A. Shluger, and T. Grasser. Microelectronics Reliability, (2018)Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling.Z. Wu, J. Franco, D. Claes, G. Rzepa, P. Roussel, N. Collaert, G. Groeseneken, D. Linten, T. Grasser, and B. Kaczer. IRPS, page 1-7. IEEE, (2019)Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors.T. Grasser, B. Stampfer, M. Waltl, G. Rzepa, K. Rupp, F. Schanovsky, G. Pobegen, K. Puschkarsky, H. Reisinger, B. O'Sullivan and 1 other author(s). IRPS, page 2. IEEE, (2018)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.B. O'Sullivan, R. Ritzenthaler, G. Rzepa, Z. Wu, E. Litta, O. Richard, T. Conard, V. Machkaoutsan, P. Fazan, C. Kim and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Characterization and modeling of reliability issues in nanoscale devices.G. Rzepa, W. Gös, B. Kaczer, and T. Grasser. ISCAS, page 2445-2448. IEEE, (2015)

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Disambiguation of "Rzepa, Gerhard"

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Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.

Please choose a person to relate this publication to

Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Rzepa, Gerhard"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.

Please choose a person to relate this publication to

Univ. -Prof. Dr. Gerhard Busse University of Stuttgart

Prof. Dr. -Ing. Gerhard Egbers University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Gumpoltsberger University of Stuttgart

Hon. -Prof. Dr. -Ing. Gerhard Bröckel University of Stuttgart

Gerhard Meißner University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.