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Disambiguation of "Alioto, Massimo"

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Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.

, , , , , , and . IEEE Trans. on Circuits and Systems, 59-II (7): 439-442 (2012)

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Other publications of authors with the same name

A Design Methodology for High-Speed Low-Power MCML Frequency Dividers., , and . ICECS, page 1308-1311. IEEE, (2006)Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers., , and . ECCTD, page 592-595. IEEE, (2011)PVT variations in differential flip-flops: A comparative analysis., , and . ECCTD, page 1-4. IEEE, (2015)Comparative soft error evaluation of layout cells in FinFET technology., , and . Microelectronics Reliability, 54 (9-10): 2300-2305 (2014)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies., , and . IEEE Trans. VLSI Syst., 19 (5): 725-736 (2011)Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.. IEEE Trans. on Circuits and Systems, 59-I (1): 3-29 (2012)Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits., , , , and . IEEE Trans. on Circuits and Systems, 62-I (2): 458-467 (2015)Power-Aware Design of Nanometer MCML Tapered Buffers., and . IEEE Trans. on Circuits and Systems, 55-II (1): 16-20 (2008)Performance evaluation of the low-voltage CML D-latch topology., , and . Integration, 36 (4): 191-209 (2003)A gate-level strategy to design Carry Select Adders., , and . ISCAS (2), page 465-468. IEEE, (2004)