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Power-Aware Design of Nanometer MCML Tapered Buffers.

, and . IEEE Trans. on Circuits and Systems, 55-II (1): 16-20 (2008)

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CML ring oscillators: oscillation frequency., , and . ISCAS (4), page 112-115. IEEE, (2001)A novel 1-V class-AB transconductor for improving speed performance in SC applications., and . ISCAS (1), page 153-156. IEEE, (2003)Design of MUX, XOR and D-latch SCL gates., and . ISCAS (5), page 261-264. IEEE, (2003)Modeling and minimization of power consumption in charge pump circuits., , and . ISCAS (4), page 402-405. IEEE, (2001)Advances in Reversed Nested Miller Compensation., , and . IEEE Trans. on Circuits and Systems, 54-I (7): 1459-1470 (2007)Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation., , , , and . IEEE Trans. on Circuits and Systems, 54-I (5): 933-940 (2007)Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates., and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 265-275. Springer, (2000)A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering., , and . ICECS, page 233-236. IEEE, (2018)Figures of merit for class AB input stages., , and . ECCTD, page 749-752. IEEE, (2011)The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation., , , and . I. J. Circuit Theory and Applications, 45 (4): 457-465 (2017)