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Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.

R. Ritzenthaler, T. Schram, E. Bury, J. Mitard, L. Ragnarsson, G. Groeseneken, N. Horiguchi, A. Thean, A. Spessot, C. Caillat, V. Srividya, and P. Fazan. ESSDERC, page 242-245. IEEE, (2012)

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Erik Eppinger University of Stuttgart

Erik Hesselmeier University of Stuttgart

Dr. Erik Poloni University of Stuttgart

Erik Wimmer University of Stuttgart

Erik-Felix Tinsel University of Stuttgart

Other publications of authors with the same name

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.P. Weckx, B. Kaczer, C. Chen, J. Franco, E. Bury, K. Chanda, J. Watt, P. Roussel, F. Catthoor, and G. Groeseneken. IRPS, page 3. IEEE, (2015)A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS.K. Chuang, E. Bury, R. Degraeve, B. Kaczer, D. Linten, and I. Verbauwhede. A-SSCC, page 157-160. IEEE, (2018)Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.R. Ritzenthaler, T. Schram, E. Bury, J. Mitard, L. Ragnarsson, G. Groeseneken, N. Horiguchi, A. Thean, A. Spessot, C. Caillat and 2 other author(s). ESSDERC, page 242-245. IEEE, (2012)Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the VG, VD bias space.E. Bury, A. Chasin, M. Vandemaele, S. Beek, J. Franco, B. Kaczer, and D. Linten. IRPS, page 1-6. IEEE, (2019)Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs.M. Vandemaele, B. Kaczer, S. Tyaginov, Z. Stanojevic, A. Makarov, A. Chasin, E. Bury, H. Mertens, D. Linten, and G. Groeseneken. IRPS, page 1-7. IEEE, (2019)Origins and implications of increased channel hot carrier variability in nFinFETs.B. Kaczer, J. Franco, M. Cho, T. Grasser, P. Roussel, S. Tyaginov, M. Bina, Y. Wimmer, L. Procel, L. Trojman and 11 other author(s). IRPS, page 3. IEEE, (2015)A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.B. Kaczer, J. Franco, P. Weckx, P. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais and 4 other author(s). Microelectronics Reliability, (2018)The defect-centric perspective of device and circuit reliability - From individual defects to circuits.B. Kaczer, J. Franco, P. Weckx, P. Roussel, E. Bury, M. Cho, R. Degraeve, D. Linten, G. Groeseneken, H. Kukner and 5 other author(s). ESSDERC, page 218-225. IEEE, (2015)Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulations.E. Bury, B. Kaczer, S. Beek, and D. Lintern. ESSDERC, page 186-189. IEEE, (2018)A multi-bit/cell PUF using analog breakdown positions in CMOS.K. Chuang, E. Bury, R. Degraeve, B. Kaczer, T. Kallstenius, G. Groeseneken, D. Linten, and I. Verbauwhede. IRPS, page 2-1. IEEE, (2018)

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Disambiguation of "Bury, Erik"

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Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.

Please choose a person to relate this publication to

Erik Eppinger University of Stuttgart

Erik Hesselmeier University of Stuttgart

Dr. Erik Poloni University of Stuttgart

Erik Wimmer University of Stuttgart

Erik-Felix Tinsel University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Bury, Erik"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.

Please choose a person to relate this publication to

Erik Eppinger University of Stuttgart

Erik Hesselmeier University of Stuttgart

Dr. Erik Poloni University of Stuttgart

Erik Wimmer University of Stuttgart

Erik-Felix Tinsel University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
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Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks.