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Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the VG, VD bias space.

E. Bury, A. Chasin, M. Vandemaele, S. Beek, J. Franco, B. Kaczer, and D. Linten. IRPS, page 1-6. IEEE, (2019)

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Adrian Schlottke University of Stuttgart

Adrian Barwasser University of Stuttgart

Adrian Eitle University of Stuttgart

PD Dr. -Ing. Adrian Pocanschi University of Stuttgart

Adrian Stock University of Stuttgart

Other publications of authors with the same name

Self-heating-aware CMOS reliability characterization using degradation maps.E. Bury, A. Chasin, B. Kaczer, K. Chuang, J. Franco, M. Simicic, P. Weckx, and D. Linten. IRPS, page 2. IEEE, (2018)Bidirectional communication in an HF hybrid organic/solution-processed metal-oxide RFID tag.K. Myny, M. Rockele, A. Chasin, D. Pham, J. Steiger, S. Botnaras, D. Weber, B. Herold, J. Ficker, B. van der Putten and 4 other author(s). ISSCC, page 312-314. IEEE, (2012)Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the VG, VD bias space.E. Bury, A. Chasin, M. Vandemaele, S. Beek, J. Franco, B. Kaczer, and D. Linten. IRPS, page 1-6. IEEE, (2019)Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects.C. Wu, A. Chasin, A. Padovani, A. Lesniewska, S. Demuynck, and K. Croes. IRPS, page 1-6. IEEE, (2019)Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs.M. Vandemaele, B. Kaczer, S. Tyaginov, Z. Stanojevic, A. Makarov, A. Chasin, E. Bury, H. Mertens, D. Linten, and G. Groeseneken. IRPS, page 1-7. IEEE, (2019)A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.B. Kaczer, J. Franco, P. Weckx, P. Roussel, V. Putcha, E. Bury, M. Simicic, A. Chasin, D. Linten, B. Parvais and 4 other author(s). Microelectronics Reliability, (2018)Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants.A. Makarov, D. Linten, S. Tyaginov, B. Kaczer, P. Roussel, A. Chasin, M. Vandemaele, G. Hellings, A. El-Sayed, M. Jech and 1 other author(s). ESSDERC, page 262-265. IEEE, (2019)Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs.A. Makarov, B. Kaczer, P. Roussel, A. Chasin, A. Grill, M. Vandemaele, G. Hellings, A. El-Sayed, T. Grasser, D. Linten and 1 other author(s). IRPS, page 1-7. IEEE, (2019)Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space.J. Franco, B. Kaczer, A. Chasin, E. Bury, and D. Linten. IRPS, page 5. IEEE, (2018)Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors.A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, J. Genoe, G. Gelinck, G. Groeseneken, and P. Heremans. ESSDERC, page 302-304. IEEE, (2014)

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Disambiguation of "Chasin, Adrian"