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Disambiguation of "Hellings, Geert"

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Stochastic Modeling of Hot-Carrier Degradation in nFinFETs Considering the Impact of Random Traps and Random Dopants.

, , , , , , , , , , and . ESSDERC, page 262-265. IEEE, (2019)

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Dr. Geert Schellenberg University of Stuttgart

 

Other publications of authors with the same name

ESD characterization of planar InGaAs devices., , , , , , , , , and 7 other author(s). IRPS, page 3. IEEE, (2015)ESD characterisation of a-IGZO TFTs on Si and foil substrates., , , , , , , , and . ESSDERC, page 276-279. IEEE, (2017)ESD protection diodes in optical interposer technology., , , , , , and . ICICDT, page 1-4. IEEE, (2015)Scaling CMOS beyond Si FinFET: an analog/RF perspective., , , , , , , , , and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology., , , , and . ESSDERC, page 194-197. IEEE, (2018)Processing active devices on Si interposer and impact on cost., , , , , , , , , and . 3DIC, page TS11.2.1-TS11.2.4. IEEE, (2015)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures., , , , , , , , and . Microelectronics Reliability, 50 (3): 360-364 (2010)Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications., , , , , , , , , and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET., , , , , , , and . Microelectronics Reliability, (2018)