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A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS., , , , , , and . J. Solid-State Circuits, 44 (11): 2873-2880 (2009)A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS., , , , and . J. Solid-State Circuits, 45 (10): 2080-2090 (2010)A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS., , , , and . J. Solid-State Circuits, 44 (3): 874-882 (2009)SWAN: high-level simulation methodology for digital substrate noise generation., , , , , and . IEEE Trans. VLSI Syst., 14 (1): 23-33 (2006)Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters., , , , and . IEICE Transactions, 92-C (6): 843-851 (2009)AMGIE-A synthesis environment for CMOS analog integrated circuits., , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (9): 1037-1058 (2001)TSV process-induced MOS reliability degradation., , , , , , and . IRPS, page 5. IEEE, (2018)3D integration: Circuit design, test, and reliability challenges., , , , , , , , and . IOLTS, page 217. IEEE Computer Society, (2010)Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study., , , , , , , , and . 3DIC, page 1-6. IEEE, (2009)Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges., , , , , , , and . 3DIC, page 1-7. IEEE, (2014)