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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , and 5 other author(s). VLSIC, page 222-. IEEE, (2015)Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs., , , , , , , , , and 1 other author(s). ESSDERC, page 330-333. IEEE, (2012)A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , and . NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)Area and routing efficiency of SWD circuits compared to advanced CMOS., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)