PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Velenis, Dimitrios"

Author of the publication

copydeleteadd this publication to your clipboard
Active-lite interposer for 2.5 & 3D integration.

, , , , , , , , , , , , , , and . VLSIC, page 222-. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dimitrios Tsoutsoulopoulos University of Stuttgart

Dimitrios Thalassinos University of Stuttgart

 

Other publications of authors with the same name

Effects of Parameter Variations on Timing Characteristics of Clocked Registers., and . Journal of Circuits, Systems, and Computers, 18 (7): 1309-1320 (2009)Cost effectiveness of 3D integration options., , and . 3DIC, page 1-6. IEEE, (2010)3D integration: Circuit design, test, and reliability challenges., , , , , , , , and . IOLTS, page 217. IEEE Computer Society, (2010)Clock tree layout design for reduced delay uncertainty., , and . SoCC, page 179-180. IEEE, (2004)Fabrication Cost Analysis for Contactless 3-D ICs., , and . IEEE Trans. on Circuits and Systems, 66-II (5): 758-762 (2019)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling., , , , , and . Journal of Circuits, Systems, and Computers, 11 (3): 231-246 (2002)Impact of 3D design choices on manufacturing cost., , , , and . 3DIC, page 1-5. IEEE, (2009)Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers., and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 508-517. Springer, (2005)Effects of process and environmental variations on timing characteristics of clocked registers., and . ACM Great Lakes Symposium on VLSI, page 165-168. ACM, (2006)