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System-level assessment and area evaluation of Spin Wave logic circuits.

O. Zografos, P. Raghavan, L. Amarù, B. Soree, R. Lauwereins, I. Radu, D. Verkest, and A. Thean. NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)

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Reconfigurable nanoscale spin wave majority gate with frequency-division multiplexing.G. Talmelli, T. Devolder, N. Träger, J. Förster, S. Wintz, M. Weigand, H. Stoll, M. Heyns, G. Schütz, I. Radu and 3 other author(s). CoRR, (2019)Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective.T. Agarwal, I. Radu, P. Raghavan, G. Fiori, A. Thean, M. Heyns, and W. Dehaene. ESSCIRC, page 55-58. IEEE, (2016)Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures.Y. Balaji, Q. Smets, C. de la Rosa, A. Lu, D. Chiappe, T. Agarwal, D. Lin, C. Huyghebaert, I. Radu, D. Mocuta and 1 other author(s). ESSDERC, page 106-109. IEEE, (2017)Area and routing efficiency of SWD circuits compared to advanced CMOS.O. Zografos, P. Raghavan, Y. Sherazi, A. Vaysset, F. Ciubatoru, B. Soree, R. Lauwereins, I. Radu, and A. Thean. ICICDT, page 1-4. IEEE, (2015)System-level assessment and area evaluation of Spin Wave logic circuits.O. Zografos, P. Raghavan, L. Amarù, B. Soree, R. Lauwereins, I. Radu, D. Verkest, and A. Thean. NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)Material selection and device design guidelines for two-dimensional materials based TFETs.T. Agarwal, B. Soree, I. Radu, P. Raghavan, G. Fiori, M. Heyns, and W. Dehaene. ESSDERC, page 54-57. IEEE, (2017)Non-volatile spin wave majority gate at the nanoscale.O. Zografos, S. Dutta, M. Manfrini, A. Vaysset, B. Sorée, A. Naeemi, P. Raghavan, R. Lauwereins, and I. Radu. CoRR, (2016)Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry.B. Gys, F. Mohiyaddin, R. Acharya, R. Li, K. Greve, G. Gielen, B. Govoreanu, I. Radu, and F. Catthoor. ESSCIRC, page 63-66. IEEE, (2021)Towards high-performance polarity-controllable FETs with 2D materials.G. Resta, J. Gonzalez, Y. Balaji, T. Agarwal, D. Lin, F. Catthoor, I. Radu, G. Micheli, and P. Gaillardon. DATE, page 637-641. IEEE, (2018)Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing.I. Radu, R. Li, A. Potocnik, T. Ivanov, D. Wan, S. Kubicek, N. Stuyck, J. Verjauw, J. Jussot, Y. Canvel and 19 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)

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System-level assessment and area evaluation of Spin Wave logic circuits.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML System-level assessment and area evaluation of Spin Wave logic circuits.

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System-level assessment and area evaluation of Spin Wave logic circuits.