PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Horiguchi, Naoto"

Author of the publication

copydeleteadd this publication to your clipboard
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.

, , , , , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Horiguchi, Naoto
add a person with the name Horiguchi, Naoto
 

Other publications of authors with the same name

PPAC scaling enablement for 5nm mobile SoC technology., , , , , , , , , and 7 other author(s). ESSDERC, page 240-243. IEEE, (2017)Off-state stress degradation mechanism on advanced p-MOSFETs., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Origins and implications of increased channel hot carrier variability in nFinFETs., , , , , , , , , and 11 other author(s). IRPS, page 3. IEEE, (2015)Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications., , , , , , , , , and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET., , , , , , , and . Microelectronics Reliability, (2018)New methodology for modelling MOL TDDB coping with variability., , , , , and . IRPS, page 3. IEEE, (2018)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)