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Assessment of SiGe quantum well transistors for DRAM peripheral applications.

R. Ritzenthaler, T. Schram, G. Eneman, A. Mocuta, N. Horiguchi, A. Thean, A. Spessot, M. Aoulaiche, P. Fazan, K. Noh, and Y. Son. ICICDT, page 1-4. IEEE, (2015)

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Dr. Geert Schellenberg University of Stuttgart

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Assessment of SiGe quantum well transistors for DRAM peripheral applications.R. Ritzenthaler, T. Schram, G. Eneman, A. Mocuta, N. Horiguchi, A. Thean, A. Spessot, M. Aoulaiche, P. Fazan, K. Noh and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)PPAC scaling enablement for 5nm mobile SoC technology.M. Badaroglu, J. Xu, J. Zhu, D. Yang, J. Bao, S. Song, P. Feng, R. Ritzenthaler, H. Mertens, G. Eneman and 7 other author(s). ESSDERC, page 240-243. IEEE, (2017)3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps.W. Guo, G. der Plas, A. Ivankovic, G. Eneman, V. Cherman, B. Wachter, A. Mercha, M. Gonzalez, Y. Civale, A. Redolfi and 9 other author(s). ICICDT, page 1-4. IEEE, (2012)FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.G. Eneman, A. Keersgieter, A. Mocuta, N. Collaert, and A. Thean. ICICDT, page 1-4. IEEE, (2015)Analysis of microbump induced stress effects in 3D stacked IC technologies.A. Ivankovic, G. der Plas, V. Moroz, M. Choi, V. Cherman, A. Mercha, P. Marchal, M. Gonzalez, G. Eneman, W. Zhang and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.G. Eneman, J. Cho, V. Moroz, D. Milojevic, M. Choi, K. Meyer, A. Mercha, E. Beyne, T. Hoffmann, and G. der Plas. DATE, page 505-506. IEEE, (2011)Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.J. Franco, B. Kaczer, J. Mitard, M. Toledano-Luque, F. Crupi, G. Eneman, P. Rousse, T. Grasser, M. Cho, T. Kauerauf and 6 other author(s). ICICDT, page 1-4. IEEE, (2012)Lateral NWFET optimization for beyond 7nm nodes.D. Yakimets, D. Jang, P. Raghavan, G. Eneman, H. Mertens, P. Schuddinck, A. Mallik, M. Bardon, N. Collaert, A. Mercha and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET.S. Yamaguchi, L. Witters, J. Mitard, G. Eneman, G. Hellings, A. Hikavyy, R. Loo, and N. Horiguchi. Microelectronics Reliability, (2018)Beyond-Si materials and devices for more Moore and more than Moore applications.N. Collaert, A. Alian, H. Arimura, G. Boccardi, G. Eneman, J. Franco, T. Ivanov, D. Lin, J. Mitard, S. Ramesh and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)

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Disambiguation of "Eneman, Geert"

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Assessment of SiGe quantum well transistors for DRAM peripheral applications.

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Dr. Geert Schellenberg University of Stuttgart

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Disambiguation of "Eneman, Geert"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Assessment of SiGe quantum well transistors for DRAM peripheral applications.

Please choose a person to relate this publication to

Dr. Geert Schellenberg University of Stuttgart

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Disambiguation

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Assessment of SiGe quantum well transistors for DRAM peripheral applications.