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Lateral NWFET optimization for beyond 7nm nodes.

D. Yakimets, D. Jang, P. Raghavan, G. Eneman, H. Mertens, P. Schuddinck, A. Mallik, M. Bardon, N. Collaert, A. Mercha, D. Verkest, A. Thean, and K. Meyer. ICICDT, page 1-4. IEEE, (2015)

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Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.T. Bao, S. Sakhare, J. Ryckaert, D. Yakimets, A. Mercha, D. Verkest, A. Thean, and P. Wambacq. ICICDT, page 1-4. IEEE, (2015)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.D. Jang, M. Bardon, D. Yakimets, K. Miyaguchi, A. Keersgieter, T. Chiarella, R. Ritzenthaler, M. Dehan, and A. Mercha. ESSDERC, page 159-162. IEEE, (2013)Technology and architecture for deep submicron RF CMOS technology.A. Mercha. SBCCI, page 4. ACM, (2005)Impact on the back gate degradation in partially depleted SOI n-MOSFETs by 2-MeV electron irradiation.K. Hayama, K. Takakura, K. Shigaki, H. Ohyama, J. Rafí, A. Mercha, E. Simoen, and C. Claeys. Microelectronics Reliability, 46 (9-11): 1731-1735 (2006)Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges.S. Decoutere, P. Wambacq, V. Subramanian, J. Borremans, and A. Mercha. CICC, page 679-686. IEEE, (2006)Design Technology co-optimization for N10.J. Ryckaert, P. Raghavan, R. Baert, M. Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, P. Wambacq, B. Chava and 18 other author(s). CICC, page 1-8. IEEE, (2014)Holisitic device exploration for 7nm node.P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta and 5 other author(s). CICC, page 1-5. IEEE, (2015)Analysis of microbump induced stress effects in 3D stacked IC technologies.A. Ivankovic, G. der Plas, V. Moroz, M. Choi, V. Cherman, A. Mercha, P. Marchal, M. Gonzalez, G. Eneman, W. Zhang and 9 other author(s). 3DIC, page 1-5. IEEE, (2011)Degradation of electrical performance and floating body effect in ultra thin gate oxide FD-SOI n-MOSFETs by 7.5-MeV proton irradiation.K. Hayama, K. Takakura, H. Ohyama, A. Mercha, E. Simoen, C. Claeys, J. Rafí, and M. Kokkoris. Microelectronics Reliability, 44 (9-11): 1721-1726 (2004)FinFET technology for analog and RF circuits.B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sanssen, G. Groeseneken, and S. Decoutere. ICECS, page 182-185. IEEE, (2007)

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Disambiguation of "Mercha, Abdelkarim"

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Lateral NWFET optimization for beyond 7nm nodes.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Lateral NWFET optimization for beyond 7nm nodes.

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Lateral NWFET optimization for beyond 7nm nodes.