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Disambiguation of "Mocuta, Anda"

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Assessment of SiGe quantum well transistors for DRAM peripheral applications.

, , , , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Anda Degeratu University of Stuttgart

 

Other publications of authors with the same name

Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies., , , , , , , , , and . IRPS, page 1-7. IEEE, (2019)Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies., , , , , and . VLSI Design, page 697-702. IEEE Computer Society, (2005)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)New methodology for modelling MOL TDDB coping with variability., , , , , and . IRPS, page 3. IEEE, (2018)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Nonparabolicity and confinement effects of IIIV materials in novel transistors., , and . ICICDT, page 1-3. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications., , , , , , , , , and 2 other author(s). DAC, page 13. ACM, (2019)