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ESD protection diodes in optical interposer technology., , , , , , and . ICICDT, page 1-4. IEEE, (2015)ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology., , , , and . ESSDERC, page 194-197. IEEE, (2018)Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices., , , , , , , , , and 6 other author(s). IRPS, page 1-8. IEEE, (2019)Extended RVS characterisation of STT-MRAM devices: Enabling detection of AP/P switching and breakdown., , , , , , , , , and 1 other author(s). IRPS, page 5-1. IEEE, (2018)Self-heating-aware CMOS reliability characterization using degradation maps., , , , , , , and . IRPS, page 2. IEEE, (2018)Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps., , , , , , and . IRPS, page 5. IEEE, (2018)Processing active devices on Si interposer and impact on cost., , , , , , , , , and . 3DIC, page TS11.2.1-TS11.2.4. IEEE, (2015)RF ESD protection strategies - the design and performance trade-off challenges., , , , , , , , , and 5 other author(s). CICC, page 489-496. IEEE, (2005)Extended Subspace Identification of Improper Linear Systems., , , and . DATE, page 454-459. IEEE Computer Society, (2004)A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability., , , , , , , , , and 4 other author(s). Microelectronics Reliability, (2018)