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I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration., , , , , , , , , and 2 other author(s). ICICDT, page 1-4. IEEE, (2015)5nm: Has the time for a device change come?, , , , , , , and . ISQED, page 275-277. IEEE, (2016)Towards high performance sub-10nm finW bulk FinFET technology., , , , , , , , , and 10 other author(s). ESSDERC, page 131-134. IEEE, (2016)Beyond-Si materials and devices for more Moore and more than Moore applications., , , , , , , , , and 16 other author(s). ICICDT, page 1-5. IEEE, (2016)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)A 7×7×2mm3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications., , , and . CICC, page 1-4. IEEE, (2019)