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How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?, , , , and . ICCAD, page 87. ACM, (2016)Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes., , , , , and . DAC, page 51:1-51:6. ACM, (2017)Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing., , , , , and . NEWCAS, page 1-4. IEEE, (2021)Power Estimation at Different Abstraction Levels for Wireless Baseband Processors., , , , and . J. Low Power Electronics, 8 (5): 726-738 (2012)An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard., , , , , , , and . SiPS, page 112-117. IEEE, (2013)Computation-skip error resilient scheme for recursive CORDIC., , , , and . SiPS, page 50-55. IEEE, (2014)Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications., , , , and . Signal Processing Systems, 84 (3): 413-424 (2016)5nm: Has the time for a device change come?, , , , , , , and . ISQED, page 275-277. IEEE, (2016)A novel positioning technique for the 2.4GHz ISM band., , , , , , and . WPNC, page 145-150. IEEE, (2009)A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited)., , , , , , , , , and 2 other author(s). GlobalSIP, page 1222-1225. IEEE, (2013)