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STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)DenTeach: A Device for Fostering Children's Good Tooth-brushing Habits., , , , and . IDC, page 619-624. ACM, (2016)Lateral NWFET optimization for beyond 7nm nodes., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Impact of fin shape variability on device performance towards 10nm node., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)5nm: Has the time for a device change come?, , , , , , , and . ISQED, page 275-277. IEEE, (2016)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes., , , , , , , , , and 5 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1039-1051 (2015)Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Holisitic device exploration for 7nm node., , , , , , , , , and 5 other author(s). CICC, page 1-5. IEEE, (2015)Scaling CMOS beyond Si FinFET: an analog/RF perspective., , , , , , , , , and 4 other author(s). ESSDERC, page 158-161. IEEE, (2018)