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Disambiguation of "Irie, Naohiko"

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An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.

, , , , , , , , , , , , and . ISSCC, page 480-481. IEEE, (2009)

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Other publications of authors with the same name

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth., , , , , , , , , and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 45 (4): 856-862 (2010)A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core., , , , , , , and . IEICE Transactions, 90-C (2): 523-530 (2007)An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM., , , , , , , , , and 3 other author(s). ISSCC, page 480-481. IEEE, (2009)Hierarchical power distribution and power management scheme for a single chip mobile processor., , , , , , , , , and 23 other author(s). DAC, page 292-295. ACM, (2006)Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration., , , , , , and . IEEE Trans. VLSI Syst., 19 (10): 1902-1907 (2011)A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption., , , , , , , , , and 4 other author(s). ISSCC, page 100-590. IEEE, (2007)Elastic shared resource scheduling SOC interconnect architecture for real-time system., , , , , , , , , and 1 other author(s). CICC, page 787-790. IEEE, (2005)Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration., , , , , , , and . IEEE Trans. VLSI Syst., 18 (8): 1238-1243 (2010)Multi-Core/Multi-IP Technology for Embedded Applications., and . IEICE Transactions, 92-C (10): 1232-1239 (2009)