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Disambiguation of "Osada, Kenichi"

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Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.

, , , , , , , and . IEEE Trans. VLSI Syst., 18 (8): 1238-1243 (2010)

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6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV., and . 3DIC, page 1-4. IEEE, (2011)Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration., , , , , , , and . IEEE Trans. VLSI Syst., 18 (8): 1238-1243 (2010)Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration., , , , and . 3DIC, page 1-6. IEEE, (2010)Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration., , , , , , and . IEEE Trans. VLSI Syst., 19 (10): 1902-1907 (2011)65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , and . ISSCC, page 384-385. IEEE, (2008)Low-Voltage Embedded RAMs - Current Status and Future Trends., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 3-15. Springer, (2004)Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters., , and . ISCAS, page 448-451. IEEE, (2012)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , and . CICC, page 701-704. IEEE, (2009)Embedded SoC Resource Manager to Control Temperature and Data Bandwidth., , , , , , , , , and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current., , , , , , , , and . ISSCC, page 474-616. IEEE, (2007)