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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core., , , , , , , , , and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core., , , , , , , , , and 1 other author(s). IEICE Transactions, 89-C (3): 287-294 (2006)Low-Power Design of 90-nm SuperH Processor Core., , , , , , , , , and 1 other author(s). ICCD, page 258-266. IEEE Computer Society, (2005)Embedded SoC Resource Manager to Control Temperature and Data Bandwidth., , , , , , , , , and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)A 45nm 37.3GOPS/W heterogeneous multi-core SoC., , , , , , , , , and 9 other author(s). ISSCC, page 100-101. IEEE, (2010)Generation of a hierarchical representation for graphic patterns based on grouping., , , , and . Systems and Computers in Japan, 24 (2): 70-87 (1993)Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 43 (4): 902-910 (2008)Design Methodology of a 200MHz Superscalar Microprocessor: SH-4., , , , , , and . DAC, page 246-249. ACM Press, (1998)