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32 Bit Instruction-Set General-Purpose Core.

O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura, H. Kasahara, and H. Maejima. IEICE Transactions, 94-C (4): 663-669 (2011)

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Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method.S. Yui, J. Miyakoshi, K. Matsuzaki, T. Irie, and R. Kurazume. Medical Imaging: Computer-Aided Diagnosis, volume 8315 of SPIE Proceedings, page 83151P. SPIE, (2012)A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.Y. Murachi, J. Miyakoshi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 91-C (4): 465-478 (2008)Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.H. Fujiwara, K. Nii, H. Noguchi, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto. IEEE Trans. VLSI Syst., 16 (6): 620-627 (2008)Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge term.J. Miyakoshi, S. Yui, K. Matsuzaki, and T. Irie. Medical Imaging: Image Processing, volume 8314 of SPIE Proceedings, page 83142C. SPIE, (2012)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)A sub-mW MPEG-4 motion estimation processor core for mobile video application.Y. Kuroda, J. Miyakoshi, M. Miyama, K. Imamura, H. Hashimoto, and M. Yoshimoto. ASP-DAC, page 527-528. IEEE Computer Society, (2004)A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, T. Ishihara, H. Kawaguchi, and M. Yoshimoto. IEICE Transactions, 89-C (11): 1629-1636 (2006)A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, H. Kawaguchi, M. Yoshimoto, and T. Matsuno. VLSI-SoC, page 192-197. IEEE, (2006)False-positive reduction of liver tumor detection using ensemble learning method.A. Miyamoto, J. Miyakoshi, K. Matsuzaki, and T. Irie. Medical Imaging: Image Processing, volume 8669 of SPIE Proceedings, page 86693B. SPIE, (2013)An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.K. Mizuno, J. Miyakoshi, Y. Murachi, M. Hamamoto, T. Iinuma, T. Ishihara, F. Yin, J. Lee, H. Kawaguchi, and M. Yoshimoto. ICECS, page 1179-1182. IEEE, (2008)

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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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Chicago
DIN 1505
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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.