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Disambiguation of "Murachi, Yuichiro"

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An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.

, , , , , , , , , and . ICECS, page 1179-1182. IEEE, (2008)

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Other publications of authors with the same name

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer., , , , , , , , and . IEICE Transactions, 91-C (4): 465-478 (2008)Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering., , , , , , , and . IEEE Trans. VLSI Syst., 16 (6): 620-627 (2008)A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing., , , , , , , and . VLSI-SoC, page 192-197. IEEE, (2006)A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing., , , , and . IEICE Transactions, 89-C (11): 1629-1636 (2006)A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application., , , , , and . IEICE Transactions, 88-A (12): 3492-3499 (2005)A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition., , , , , , , , and . IEICE Transactions, 91-C (4): 457-464 (2008)An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding., , , , , , , , , and . ICECS, page 1179-1182. IEEE, (2008)A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation., , , , , and . IEICE Transactions, 88-C (4): 559-569 (2005)A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture., , , , , , , , and . IEICE Transactions, 89-A (12): 3623-3633 (2006)A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding., , , , , , , , , and 1 other author(s). ISCAS, page 848-851. IEEE, (2008)