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32 Bit Instruction-Set General-Purpose Core.

O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura, H. Kasahara, and H. Maejima. IEICE Transactions, 94-C (4): 663-669 (2011)

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SH4 RISC multimedia microprocessor.F. Arakawa, O. Nishii, K. Uchiyama, and N. Nakagawa. IEEE Micro, 18 (2): 26-34 (1998)Low-Power Design of 90-nm SuperH Processor Core.T. Yamada, M. Abe, Y. Nitta, K. Ogura, M. Kusaoke, M. Ishikawa, M. Ozawa, K. Takada, F. Arakawa, O. Nishii and 1 other author(s). ICCD, page 258-266. IEEE Computer Society, (2005)SH-X: An embedded processor core for consumer appliances.F. Arakawa, M. Ishikawa, Y. Kondo, T. Kamei, O. Nishii, and T. Hattori. J. Embedded Computing, 2 (1): 83-90 (2006)An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.M. Ito, T. Hattori, Y. Yoshida, K. Hayase, T. Hayashi, O. Nishii, Y. Yasu, A. Hasegawa, M. Takada, H. Mizuno and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.T. Yamada, M. Abe, Y. Nitta, K. Ogura, M. Kusaoke, M. Ishikawa, M. Ozawa, K. Takada, F. Arakawa, O. Nishii and 1 other author(s). IEICE Transactions, 89-C (3): 287-294 (2006)A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption.Y. Yoshida, T. Kamei, K. Hayase, S. Shibahara, O. Nishii, T. Hattori, A. Hasegawa, M. Takada, N. Irie, K. Uchiyama and 4 other author(s). ISSCC, page 100-590. IEEE, (2007)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Low Power Platform for Embedded Processor LSIs.T. Shimizu, K. Arimoto, O. Nishii, S. Otani, and H. Kondo. IEICE Transactions, 94-C (4): 394-400 (2011)A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems.T. Okada, S. Narita, O. Nishii, N. Hiratsuka, N. Hayashi, M. Asai, S. Fujiwara, M. Satoh, J. Nishimoto, H. Aoki and 9 other author(s). COMPCON, page 47-52. IEEE Computer Society, (1994)SH-X: an embedded processor core for consumer appliances.F. Arakawa, M. Ishikawa, Y. Kondo, T. Kamei, M. Ozawa, O. Nishii, and T. Hattori. MEDEA@PACT, page 33-40. ACM, (2004)

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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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Disambiguation of "Nishii, Osamu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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URL
DOI
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APA
Chicago
DIN 1505
Harvard
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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.