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32 Bit Instruction-Set General-Purpose Core.

O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura, H. Kasahara, and H. Maejima. IEICE Transactions, 94-C (4): 663-669 (2011)

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Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.T. Yamada, M. Abe, Y. Nitta, K. Ogura, M. Kusaoke, M. Ishikawa, M. Ozawa, K. Takada, F. Arakawa, O. Nishii and 1 other author(s). IEICE Transactions, 89-C (3): 287-294 (2006)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.O. Nishii, Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, M. Ishikawa, T. Yamada, J. Miyakoshi, Y. Wada, K. Kimura and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Embedded SoC Resource Manager to Control Temperature and Data Bandwidth.M. Saen, K. Osada, S. Misaka, T. Yamada, Y. Tsujimoto, Y. Kondo, T. Kamei, Y. Yoshida, E. Nagahama, Y. Nitta and 3 other author(s). ISSCC, page 296-604. IEEE, (2007)Low-Power Design of 90-nm SuperH Processor Core.T. Yamada, M. Abe, Y. Nitta, K. Ogura, M. Kusaoke, M. Ishikawa, M. Ozawa, K. Takada, F. Arakawa, O. Nishii and 1 other author(s). ICCD, page 258-266. IEEE Computer Society, (2005)Generation of a hierarchical representation for graphic patterns based on grouping.M. Soga, J. Toyoda, Y. Nitta, T. Imanaka, and M. Yanagida. Systems and Computers in Japan, 24 (2): 70-87 (1993)A 45nm 37.3GOPS/W heterogeneous multi-core SoC.Y. Yuyama, M. Ito, Y. Kiyoshige, Y. Nitta, S. Matsui, O. Nishii, A. Hasegawa, M. Ishikawa, T. Yamada, J. Miyakoshi and 9 other author(s). ISSCC, page 100-101. IEEE, (2010)Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.H. Shikano, M. Ito, M. Onouchi, T. Todaka, T. Tsunoda, T. Kodama, K. Uchiyama, T. Odaka, T. Kamei, E. Nagahama and 5 other author(s). J. Solid-State Circuits, 43 (4): 902-910 (2008)Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.T. Hattori, Y. Nitta, M. Seki, S. Narita, K. Uchiyama, T. Takahashi, and R. Satomura. DAC, page 246-249. ACM Press, (1998)

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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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Other publications of authors with the same name

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PUMA

Disambiguation of "Nitta, Yusuke"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

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Disambiguation

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URL
DOI
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APA
Chicago
DIN 1505
Harvard
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A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.