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Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.

, , , , , , and . IEEE Trans. VLSI Syst., 19 (10): 1902-1907 (2011)

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Wireless proximity interfaces with a pulse-based inductive coupling technique., and . IEEE Communications Magazine, 48 (10): 192-199 (2010)Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration., , , , , , and . IEEE Trans. VLSI Syst., 19 (10): 1902-1907 (2011)Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation., , , and . IEEE Trans. on Circuits and Systems, 62-II (8): 726-730 (2015)A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface., , , , , , , , , and 1 other author(s). IEEE Micro, 33 (6): 6-15 (2013)A versatile recognition processor employing Haar-like feature and cascaded classifier., , , and . ISSCC, page 148-149. IEEE, (2009)A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line., , , , , , and . ISSCC, page 52-54. IEEE, (2012)6W/25mm2 inductive power transfer for non-contact wafer-level testing., , , , , , and . ISSCC, page 230-232. IEEE, (2011)A 12Gb/s non-contact interface with coupled transmission lines., , , , , and . ISSCC, page 492-494. IEEE, (2011)An 11Gb/s Inductive-Coupling Link with Burst Transmission., , , , , and . ISSCC, page 298-299. IEEE, (2008)Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design., and . VLSI Signal Processing, 13 (2-3): 191-201 (1996)