Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.
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%0 Journal Article
%1 journals/tvlsi/NiitsuSKOIIK11
%A Niitsu, Kiichi
%A Sugimori, Yasufumi
%A Kohama, Yoshinori
%A Osada, Kenichi
%A Irie, Naohiko
%A Ishikuro, Hiroki
%A Kuroda, Tadahiro
%D 2011
%J IEEE Trans. VLSI Syst.
%K dblp
%N 10
%P 1902-1907
%T Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#NiitsuSKOIIK11
%V 19
@article{journals/tvlsi/NiitsuSKOIIK11,
added-at = {2011-08-18T00:00:00.000+0200},
author = {Niitsu, Kiichi and Sugimori, Yasufumi and Kohama, Yoshinori and Osada, Kenichi and Irie, Naohiko and Ishikuro, Hiroki and Kuroda, Tadahiro},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28a591cfa6ecc116f523fa2538428cf32/dblp},
ee = {http://dx.doi.org/10.1109/TVLSI.2010.2056711},
interhash = {407706a52812640f74cb6c484df226bb},
intrahash = {8a591cfa6ecc116f523fa2538428cf32},
journal = {IEEE Trans. VLSI Syst.},
keywords = {dblp},
number = 10,
pages = {1902-1907},
timestamp = {2016-02-02T02:13:15.000+0100},
title = {Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#NiitsuSKOIIK11},
volume = 19,
year = 2011
}
