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A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.

N. Miura, Y. Koizumi, Y. Take, H. Matsutani, T. Kuroda, H. Amano, R. Sakamoto, M. Namiki, K. Usami, M. Kondo, and H. Nakamura. IEEE Micro, 33 (6): 6-15 (2013)

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Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping.H. Sasaki, M. Kondo, and H. Nakamura. IEEE Trans. VLSI Syst., 17 (6): 848-852 (2009)Skewed Checkpointing for Tolerating Multi-Node Failures.H. Nakamura, T. Hayashida, M. Kondo, Y. Tajima, M. Imai, and T. Nanya. SRDS, page 116-125. IEEE Computer Society, (2004)Cool Mega-Array: A highly energy efficient reconfigurable accelerator.N. Ozaki, Y. Yasuda, Y. Saito, D. Ikebuchi, M. Kimura, H. Amano, H. Nakamura, K. Usami, M. Namiki, and M. Kondo. FPT, page 1-8. IEEE, (2011)Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units.Z. Lei, D. Ikebuchi, K. Usami, M. Namiki, M. Kondo, H. Nakamura, and H. Amano. IPSJ Trans. System LSI Design Methodology, (2011)Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.Y. Koizumi, N. Miura, Y. Take, H. Matsutani, T. Kuroda, H. Amano, R. Sakamoto, M. Namiki, K. Usami, M. Kondo and 1 other author(s). FPL, page 1. IEEE, (2013)Runtime multi-optimizations for energy efficient on-chip interconnections1.Y. He, M. Kondo, T. Nakada, H. Sasaki, S. Miwa, and H. Nakamura. ICCD, page 455-458. IEEE Computer Society, (2015)Opportunistic circuit-switching for energy efficient on-chip networks.Y. He, and M. Kondo. VLSI-SoC, page 1-6. IEEE, (2016)A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units.A. Koshiba, M. Wada, R. Sakamoto, M. Sato, T. Kosaka, K. Usami, H. Amano, M. Kondo, H. Nakamura, and M. Namiki. IEICE Transactions, 98-C (7): 559-568 (2015)An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications.A. Koshiba, M. Sato, K. Usami, H. Amano, R. Sakamoto, M. Kondo, H. Nakamura, and M. Namiki. IEICE Transactions, 99-C (8): 926-935 (2016)Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.H. Nakamura, M. Kondo, and T. Boku. Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 15-32. Springer, (2000)

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A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.

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A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.