%0 Journal Article %1 journals/tvlsi/NiitsuKSKOIIK10 %A Niitsu, Kiichi %A Kohama, Yoshinori %A Sugimori, Yasufumi %A Kasuga, Kazutaka %A Osada, Kenichi %A Irie, Naohiko %A Ishikuro, Hiroki %A Kuroda, Tadahiro %D 2010 %J IEEE Trans. VLSI Syst. %K dblp %N 8 %P 1238-1243 %T Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#NiitsuKSKOIIK10 %V 18

@article{journals/tvlsi/NiitsuKSKOIIK10, added-at = {2011-02-15T00:00:00.000+0100}, author = {Niitsu, Kiichi and Kohama, Yoshinori and Sugimori, Yasufumi and Kasuga, Kazutaka and Osada, Kenichi and Irie, Naohiko and Ishikuro, Hiroki and Kuroda, Tadahiro}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/26fac89265c11e5b316cd93b71858ee6a/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2009.2020724}, interhash = {9ecd8d87a77f215e54feac7347cf246b}, intrahash = {6fac89265c11e5b316cd93b71858ee6a}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 8, pages = {1238-1243}, timestamp = {2016-02-02T02:13:41.000+0100}, title = {Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#NiitsuKSKOIIK10}, volume = 18, year = 2010 }