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Disambiguation of "Hattori, Toshihiro"

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An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.

, , , , , , , , , , , , and . ISSCC, page 480-481. IEEE, (2009)

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Other publications of authors with the same name

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems., , , , , , , , , and . ISSCC, page 78-79. IEEE, (2016)A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management., , , , , , , and . ASP-DAC, page 535-539. IEEE, (2009)An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler., , , , , , , , , and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)Low-Power Design of 90-nm SuperH Processor Core., , , , , , , , , and 1 other author(s). ICCD, page 258-266. IEEE Computer Society, (2005)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 45 (4): 856-862 (2010)Beyond the red brick wall (panel): challenges and solutions in 50nm physical design., , , , , , and . ASP-DAC, page 267-268. ACM, (2001)Design methodology of low-power microprocessors.. ASP-DAC, page 390-393. ACM, (2003)A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 50 (1): 92-101 (2015)Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core., , , , , , , , , and 1 other author(s). IEICE Transactions, 89-C (3): 287-294 (2006)A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption., , , , , , , , , and 4 other author(s). ISSCC, page 100-590. IEEE, (2007)