Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Shimazaki, Yasuhisa
add a person with the name Shimazaki, Yasuhisa
 

Other publications of authors with the same name

65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS., , , and . ISSCC, page 384-385. IEEE, (2008)A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D., , , , , , , , , and 3 other author(s). ISSCC, page 54-56. IEEE, (2019)A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 55 (1): 133-144 (2020)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability., , , , , , , and . ISSCC, page 80-81. IEEE, (2016)A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors., , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 42 (1): 74-83 (2007)A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS., , , , , , and . J. Solid-State Circuits, 48 (4): 917-923 (2013)3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 45 (4): 856-862 (2010)A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation., , , , , and . CICC, page 701-704. IEEE, (2009)An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM., , , , , , , , , and 3 other author(s). ISSCC, page 480-481. IEEE, (2009)