%0 Conference Paper %1 conf/coolchips/ShimazakiMK12 %A Shimazaki, Yasuhisa %A Miura, Noriyuki %A Kuroda, Tadahiro %B COOL Chips %D 2012 %E Kobayashi, Hiroaki %E Ikeda, Makoto %E Arakawa, Fumio %I IEEE Computer Society %K dblp %P 1-3 %T A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. %U http://dblp.uni-trier.de/db/conf/coolchips/coolchips2012.html#ShimazakiMK12 %@ 978-1-4673-1201-1

@inproceedings{conf/coolchips/ShimazakiMK12, added-at = {2019-02-21T00:00:00.000+0100}, author = {Shimazaki, Yasuhisa and Miura, Noriyuki and Kuroda, Tadahiro}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2f7c562f99bcd5d85c6a6cb678420462f/dblp}, booktitle = {COOL Chips}, crossref = {conf/coolchips/2012}, editor = {Kobayashi, Hiroaki and Ikeda, Makoto and Arakawa, Fumio}, ee = {http://doi.ieeecomputersociety.org/10.1109/COOLChips.2012.6216583}, interhash = {4dcc42b76772c7c02e5468478738a3a8}, intrahash = {f7c562f99bcd5d85c6a6cb678420462f}, isbn = {978-1-4673-1201-1}, keywords = {dblp}, pages = {1-3}, publisher = {IEEE Computer Society}, timestamp = {2019-09-27T16:20:43.000+0200}, title = {A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.}, url = {http://dblp.uni-trier.de/db/conf/coolchips/coolchips2012.html#ShimazakiMK12}, year = 2012 }