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4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.

C. Takahashi, S. Shibahara, K. Fukuoka, J. Matsushima, Y. Kitaji, Y. Shimazaki, H. Hara, and T. Irita. ISSCC, page 80-81. IEEE, (2016)

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A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems.S. Mochizuki, K. Matsubara, K. Matsumoto, C. Nguyen, T. Shibayama, K. Iwata, K. Mizumoto, T. Irita, H. Hara, and T. Hattori. IEICE Transactions, 100-A (12): 2878-2887 (2017)4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.C. Takahashi, S. Shibahara, K. Fukuoka, J. Matsushima, Y. Kitaji, Y. Shimazaki, H. Hara, and T. Irita. ISSCC, page 80-81. IEEE, (2016)Practical Experiences of Designing a Distributed Collaborative System.T. Ookubo, T. Matsutsuka, Y. Nomura, H. Hara, and S. Uehara. EDOC, page 21-. IEEE Computer Society, (2000)Model-Based Architecture for the Intranet.H. Hara, T. Matsutsuka, N. Kanaya, T. Ookubo, and S. Uehara. COMPSAC, page 182-187. IEEE Computer Society, (1997)An Optimistic Method for Updating Information in Distributed Collaborative Work.T. Okubo, T. Matsutsuka, Y. Tanaka, H. Hara, and S. Uehara. COMPSAC, page 400-405. IEEE Computer Society, (1998)A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard.S. Shibahara, C. Takahashi, K. Fukuoka, Y. Kitaji, T. Irita, H. Hara, Y. Shimazaki, and J. Matsushima. J. Solid-State Circuits, 52 (1): 77-88 (2017)4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems.S. Mochizuki, K. Matsubara, K. Matsumoto, C. Nguyen, T. Shibayama, K. Iwata, K. Mizumoto, T. Irita, H. Hara, and T. Hattori. ISSCC, page 78-79. IEEE, (2016)Distributed Workflow Management System for Electronic Commerce.N. Kanaya, H. Hara, Y. Nomura, H. Komori, and T. Ebata. EDOC, page 150-159. IEEE Computer Society, (2000)Enterprise model-based software architecture with server component integration.S. Uehara, H. Hara, N. Kanaya, T. Ookubo, and T. Matsutsuka. EDOC, page 356-363. IEEE, (1998)Collaboration Management Framework for Integrating B-to-B and Internal Processes.K. Yano, H. Hara, and S. Uehara. EDOC, page 75-83. IEEE Computer Society, (2002)

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4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.

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Disambiguation of "Hara, Hirotaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.

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4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10-7 random hardware failures per hour reliability.