PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Ito, Masayuki"

Author of the publication

copydeleteadd this publication to your clipboard
Hierarchical power distribution and power management scheme for a single chip mobile processor.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . DAC, page 292-295. ACM, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Ito, Masayuki
add a person with the name Ito, Masayuki
 

Other publications of authors with the same name

Bari-bari-II: Jack-up rescue robot with debris opening function., , , , , and . ICRA, page 2209-2210. IEEE, (2008)Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition., , and . ICCD, page 21-. IEEE Computer Society, (2003)A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 44 (1): 83-89 (2009)A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core., , , , , , , , , and 2 other author(s). IEICE Transactions, 94-C (4): 663-669 (2011)Efficient Initial Approximation and Fast Converging Methods for Division and Square Root., , and . IEEE Symposium on Computer Arithmetic, page 2-8. IEEE Computer Society, (1995)An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler., , , , , , , , , and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management., , , , , , , and . ASP-DAC, page 535-539. IEEE, (2009)Square Rooting by Iterative Multiply-Additions., , and . Inf. Process. Lett., 60 (5): 267-269 (1996)A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 274-602. IEEE, (2007)Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 9 (8): 868-875 (1990)