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Robust System Design to Overcome CMOS Reliability Challenges.

, , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 30-41 (2011)

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A Design Diversity Metric and Analysis of Redundant Systems., , and . IEEE Trans. Computers, 51 (5): 498-510 (2002)Recent Advances and New Avenues in Hardware-Level Reliability Support., , , and . IEEE Micro, 25 (6): 18-29 (2005)Fast Run-Time Fault Location in Dependable FPGA-Based Applications., , and . DFT, page 206-214. IEEE Computer Society, (2001)Testing Digital Circuits with Constraints., , and . DFT, page 195-206. IEEE Computer Society, (2002)Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics., , , , , , , , and . CICC, page 1-4. IEEE, (2013)Optimized reseeding by seed ordering and encoding., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (2): 264-270 (2005)Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection., , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (10): 1573-1590 (2014)Cross layer resiliency in real world., , , and . DATE, page 1. European Design and Automation Association, (2014)Cross-layer resilience challenges: Metrics and optimization., , and . DATE, page 1029-1034. IEEE, (2010)Bug localization techniques for effective post-silicon validation., , , and . ASP-DAC, page 291. IEEE, (2012)