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Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection.

, , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (10): 1573-1590 (2014)

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A Class of Irredundant Encoding Techniques for Reducing Bus Power., , and . Journal of Circuits, Systems, and Computers, 11 (5): 445-458 (2002)ALBORZ: Address Level Bus Power Optimization., , and . ISQED, page 470-475. IEEE Computer Society, (2002)Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis., , and . ASAP, page 202-212. IEEE Computer Society, (2004)Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (4): 478-489 (2009)Solving covering problems using LPR-based lower bounds., , and . IEEE Trans. VLSI Syst., 8 (1): 9-17 (2000)Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (10): 2012-2022 (2006)Event-driven observability enhanced coverage analysis of C programs for functional validation., , and . ASP-DAC, page 123-128. ACM, (2003)A non-uniform cache architecture for low power system design., and . ISLPED, page 363-368. ACM, (2005)Low-power fanout optimization using multiple threshold voltage inverters., , and . ISLPED, page 95-98. ACM, (2005)Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability., , and . DAC, page 528-533. ACM Press, (1998)