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Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.

, , , , , , , , and . CICC, page 1-4. IEEE, (2013)

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Frequency and yield optimization using power gates in power-constrained designs., , , , , , and . ISLPED, page 121-126. ACM, (2009)Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics., , , , , , , , and . CICC, page 1-4. IEEE, (2013)Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design., , and . ASP-DAC, page 581-586. IEEE, (2010)Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits., , and . DAC, page 103-106. IEEE, (2007)Synthesis and implementation of active mode power gating circuits., , and . DAC, page 487-492. ACM, (2010)Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating., , , and . IEEE Trans. VLSI Syst., 20 (10): 1885-1890 (2012)Synthesis of Active-Mode Power-Gating Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (3): 391-403 (2012)Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (11): 1956-1968 (2008)Design and Optimization of Power-Gated Circuits With Autonomous Data Retention., and . IEEE Trans. VLSI Syst., 19 (2): 227-236 (2011)Early-life-failure detection using SAT-based ATPG., , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)