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Disambiguation of "Bae, Seung-Jun"

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.

, , , , , , , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 43 (1): 121-131 (2008)

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Jun Chen University of Stuttgart

Jun Chen University of Stuttgart

Mathias Jung University of Stuttgart

Stefan Baehr University of Stuttgart

Jong Hyun Jung University of Stuttgart

 

Other publications of authors with the same name

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator., , , , and . IEEE Trans. on Circuits and Systems, 62-I (10): 2495-2503 (2015)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). J. Solid-State Circuits, 46 (1): 107-118 (2011)A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s., , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). J. Solid-State Circuits, 43 (1): 121-131 (2008)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 53 (10): 2906-2916 (2018)A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN., , , , , , and . J. Solid-State Circuits, 44 (11): 3146-3162 (2009)A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces., , , , , , and . ISSCC, page 138-139. IEEE, (2009)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)