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Disambiguation of "Oh, Tae-Young"

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.

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Bruno Ohngemach University of Stuttgart

Kathrin Ohmer University of Stuttgart

Sophie Ohnmacht University of Stuttgart

Peter Ohlhausen University of Stuttgart

Moon Young Jeong University of Stuttgart

 

Other publications of authors with the same name

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). J. Solid-State Circuits, 50 (1): 178-190 (2015)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (1): 157-166 (2020)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). J. Solid-State Circuits, 46 (1): 107-118 (2011)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery., , , , and . CICC, page 745-748. IEEE, (2006)AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections., , and . ISQED, page 326-330. IEEE Computer Society, (2002)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems., , , , and . IEEE Trans. on Circuits and Systems, 61-I (3): 680-688 (2014)