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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.

, , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 55 (1): 157-166 (2020)

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A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation., , , , and . ISSCC, page 398-399. IEEE, (2009)A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 41 (4): 831-838 (2006)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (1): 157-166 (2020)A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme., , , , , , , , , and 18 other author(s). J. Solid-State Circuits, 48 (1): 168-177 (2013)An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme., , , , , , , and . ISSCC, page 410-411. IEEE, (2013)A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme., , , , , , , , , and 9 other author(s). ISSCC, page 44-46. IEEE, (2012)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth., , , , , and . IEEE Trans. on Circuits and Systems, 61-II (3): 153-157 (2014)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)