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Disambiguation of "Chung, Hoeju"

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A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques.

, , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 41 (4): 831-838 (2006)

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Phi-Long Chung University of Stuttgart

 

Other publications of authors with the same name

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 41 (4): 831-838 (2006)A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth., , , , , , , , , and 20 other author(s). ISSCC, page 46-48. IEEE, (2012)A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW., , , , , , , , , and 25 other author(s). ISSCC, page 500-502. IEEE, (2011)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)8Gb 3D DDR3 DRAM using through-silicon-via technology., , , , , , , , , and 14 other author(s). ISSCC, page 130-131. IEEE, (2009)HBM3 RAS: Enhancing Resilience at Scale., , , , , , , , and . IEEE Comput. Archit. Lett., 20 (2): 158-161 (2021)8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology., , , , , , , , , and 11 other author(s). J. Solid-State Circuits, 45 (1): 111-119 (2010)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). J. Solid-State Circuits, 50 (1): 178-190 (2015)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 42 (1): 193-200 (2007)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)