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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.

, , , , , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 50 (1): 178-190 (2015)

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SoC R&D Trend for Future Digital Life.. IEICE Transactions, 88-C (8): 1705-1710 (2005)DocT - Document management and testing tool for robot software., , and . URAI, page 413-416. IEEE, (2014)A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme., , , , , , , , , and 18 other author(s). J. Solid-State Circuits, 48 (1): 168-177 (2013)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). J. Solid-State Circuits, 50 (1): 178-190 (2015)A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 42 (11): 2369-2377 (2007)Learning a Structured Graphical Model with Boosted Top-Down Features for Ultrasound Image Segmentation., , , , , , , and . MICCAI (1), volume 8149 of Lecture Notes in Computer Science, page 227-234. Springer, (2013)ISP (Information Strategy Planning) for 4S-Based Integration of Spatial Information Systems as Korean Nationwide Project., , , and . EGOV, volume 2739 of Lecture Notes in Computer Science, page 351-354. Springer, (2003)Low power requirements for future digital life style.. ISLPED, page 1. ACM, (2003)"Eat What You Want and Be Healthy!": Comfort Food Effects: Human-Food Interaction in View of Celebratory Technology., , , , , and . MHFI@ICMI, page 4:1-4:8. ACM, (2018)A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme., , , , , , , , , and 18 other author(s). ISSCC, page 38-40. IEEE, (2012)