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Disambiguation of "Yu, Xueyi"

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A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.

, , , , and . ISSCC, page 398-399. IEEE, (2009)

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Wei Yu University of Stuttgart

Bo Hung Yu University of Stuttgart

Yiwen Yuan University of Stuttgart

Xingyao Yu University of Stuttgart

Yu Li University of Stuttgart

 

Other publications of authors with the same name

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications., , , , , and . J. Solid-State Circuits, 44 (8): 2193-2201 (2009)A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction., , , , , , , , and . J. Solid-State Circuits, 55 (3): 602-614 (2020)A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation., , , , and . ISSCC, page 398-399. IEEE, (2009)An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators., , , and . J. Solid-State Circuits, 44 (9): 2426-2436 (2009)A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning., , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2149-2158 (2011)A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation., , , , , and . ISCAS, page 1179-1182. IEEE, (2013)A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications., , , , , and . CICC, page 753-756. IEEE, (2008)A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider., , , and . ISCAS, page 3051-3054. IEEE, (2007)Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL., , , and . ISCAS, page 2401-2404. IEEE, (2009)A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops., , , , , , and . J. Solid-State Circuits, 44 (11): 2922-2934 (2009)